The present disclosure relates generally to semiconductor devices, and more particularly, to the utilization of reconfigurable multi-project wafer (MPW) semiconductors to reduce the time to market, development costs, and risk inherent in today's “system on a chip” designs.
As semiconductor process technology migrates into the deep sub-micron geometries, and “system on a chip” designs become much more complex, the process steps, development time, costs, and technical risk to develop these circuit designs grow exponentially. A complex circuit may require digital signal processing, Ethernet, memory, high speed input/output modules, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), or other unique circuitry. In the conventional circuit chip design approach, each of these modules must be designed and verified prior to integration into the circuit. The operational performance of the circuit can only then be verified. Circuit developers expend an enormous amount of time and money for prototyping these devices and getting them into production. The performance of deep sub-micron devices can be adversely affected by the effects of cross-talk, electro-migration, wire delay, etc. that may present additional technical risk to the development schedule. This process results in time consuming mask and wafer iteration runs leading to long time to market, high and growing development costs, increased process steps, and increased technical risk.
It is, therefore, desirable to introduce additional standard designs that may be used in a plurality of production processes, leaving customization in the last few production steps, thereby saving production cost and time. Desirable in the art of “system on a chip” circuit designs, is a more time/cost efficient methodology to develop prototype and production circuits to decrease the product's time to market by using cost sharing reconfigurable modules.